1. Field of the Invention
The present invention relates to a Static Random Access Memory (SRAM) device and more particularly to a circuit for controlling a power supply voltage for use in the SRAM device.
2. Description of Prior Arts
The SRAM device, among various other MOS memory devices, has been widely used in the field and manufactured with high integration in its scale. In general, the high integration of the SRAM device continuously requires more scaling-down of memory cells. The SRAM device being currently used, generally adopts 5 volts of external power supply voltage, in which a voltage which is the same as the external power supply voltage is supplied to the internal memory cells of the SRAM device. In such an arrangement, when MOS transistors in the memory cells are continuously supplied with the power supply voltage during a long period of time, there frequently arises a failure problem in the MOS transistors. This drawback can be made worse owing to supplying the external power supply voltage at a higher than a normal power supply voltage, and increasing the memory capacity, thereby consequently leading to a deterioration of reliability in the memory device.
To solve the reliability problem, prior-art technology has disclosed a method in which the internal power supply voltage is lowered to about 3 volts below the 5 volts. However, though the method can reduce the reliability problem of the memory cell according to the power source voltage, there still remain other problems unsolved, such as the decrease of operational speed in the memory device as well as the destruction of data stored in the memory cell, that is, the soft-error, due to the radioactive particle from a package of semiconductor memory device.